c - STM32 odd timer1 behavior in Master-Slave Configuration - mb code issue -


i'm working on embedded system meant output specific pulse sequence @ equidistant timings. therefore, use stm32 - disco board freertos kernel, first test. configured tim3 master triggering tim1. tim1 triggered frequency of 1hz or every second. tim3 generates pulse sequence on it's output. configured tim3 output pb4, , tim1 pa9. configuration works expected, wanted change configuration on fly structure stores settings , can passed pointer function configures both timers.

as first step, generated data structure , initialized in timer function configure tim3.

pg_err tim_master_init(void){  pg_handletypedef hpg_timer; hpg_timer.pls.prescaler = 139; hpg_timer.pls.period = 60000; hpg_timer.pls.dutycycle = 30000; hpg_timer.pls.repetitioncounter = 5; hpg_timer.pls.percentchange = 0;  /* timer3 handler declaration: master */ tim_handletypedef           timmasterhandle;  /* master configuration structure */ tim_masterconfigtypedef smasterconfig;  /* output compare structure */ tim_oc_inittypedef          socconfig;  __tim3_clk_enable();  pg_err xpgerr = pg_err_none; /* compute prescaler value have tim3 counter clock equal 60 khz */  /* set timx instance */ timmasterhandle.instance = master_tim; /* master configuration: tim3  */ timmasterhandle.init.period = 60000 - 1; timmasterhandle.init.prescaler = 1399; timmasterhandle.init.clockdivision = 0; timmasterhandle.init.countermode = tim_countermode_up; if (hal_tim_pwm_init(&timmasterhandle) != hal_ok){     xpgerr = pg_err_tim; }  /* configure pwm_channel_1  */ socconfig.ocmode     = tim_ocmode_pwm1; socconfig.ocpolarity = tim_ocpolarity_high; socconfig.ocfastmode = tim_ocfast_enable; socconfig.pulse = 30000;  if (hal_tim_pwm_configchannel(&timmasterhandle, &socconfig, tim_channel_1) != hal_ok){     xpgerr = pg_err_tim; }  /* configure tim3 master & use update event trigger output (trgo) */ smasterconfig.masteroutputtrigger = tim_trgo_oc1ref; smasterconfig.masterslavemode           = tim_masterslavemode_enable; if(hal_timex_masterconfigsynchronization(&timmasterhandle, &smasterconfig) != hal_ok){     xpgerr = pg_err_tim; }         /* start pwm timer3*/ if(hal_tim_pwm_start(&timmasterhandle, tim_channel_1) != hal_ok){     xpgerr = pg_err_tim; }  if(hal_tim_base_start_it(&timmasterhandle) != hal_ok){     xpgerr = pg_err_tim; }  return xpgerr; }

1) configuration odd behaviour. after including data structure:

pg_handletypedef hpg_timer; hpg_timer.pls.prescaler = 139; hpg_timer.pls.period = 60000; hpg_timer.pls.dutycycle = 30000; hpg_timer.pls.repetitioncounter = 5; hpg_timer.pls.percentchange = 0;

after code snipped, don't output on pin pb4 (master - tim3) should still toggled @ 1hz.

2) more confusing, when substitute code block handle:

pg_handletypedef hpg_timer; pg_handletypedef *hpg_timer; hpg_timer = &hpg_timer_config; hpg_timer.pls.prescaler = 139; hpg_timer.pls.period = 60000; hpg_timer.pls.dutycycle = 30000; hpg_timer.pls.repetitioncounter = 5; hpg_timer.pls.percentchange = 0;

now can see output on pb4 (master - tim3) 1hz output polarity of pa9 (slave - tim1) reversed.

i tried investigate problem, focused on stack/heap of freertos. tested system large heap/stack = (uint32_t) 65535; couldn't observe changes in behaviour.

i hope came across similar problem or has idea how resolve this. i'm thankful input in this, i'm @ end of knowledge unfortunately.

edit: spend more time problem, , think can more specific. in case of pointer use, timmasterhandle locked right after initialization. if unlock handle timmasterhandle.lock = hal_unlock; works well, masking problem , know coming from.

it how looks still heap or stack problem. there way, can check heap or stack overflow. using keil uvision 5.10.

thank time , help,

eimer

so contacted e-mail support of st.

the rather simple answer got -

initialize timer handles e.g.:

pg_handletypedef hpg_timer = {0};

seems resolve odd behaviour.

i hope finds usefull.

enjoy day eimer


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