buffer - Canonical term for "simultaneous data-latching" -

i have module (in case on fpga) several input values (registers) updated sequentially (if @ all), copied in parallel in single, atomic step guarantee coherency during following data processing steps. there common term this?

• "double-buffering" comes close, refers 2 buffers in parallel swapped, while i'm copying them "forward".
• "simultaneous data-latching" i'm using @ moment, sounds unfamiliar...

illustration

               store_1             store_all             do_stuff                   |                    |                     |                                                +-+-+                +-+-+                 +-+-+                                           value_1 -->  |reg| --- int_1 -->  |reg| --> input_1 --> | m |                                                                           +---+                +---+                 | o |                                                                            |                   | d |                store_2                 |                   | u | --> outputs                                                |                    |                   | l |                                                 +-+-+                +-+-+                 | e |                                        value_2 -->  |reg| --- int_2 -->  |reg| --> input_2 --> |   |                                                                            +---+                +---+                 +---+                                                      __  ____________________     value_1      __><____________________              store_1      ______|_________________                                                                                                          _______  _______________     input_1      _______><_______________                    __________  ____________     value_2      __________><____________                                                                                            store_2      ______________|_________                                                                  _______________  _______     input_2      _______________><_______        store_all    ____________________|___                   _____________________  _     out_1        _____________________><_                   _____________________  _     out_2        _____________________><_       do_stuff     _______________________| 

here store_1, store_2 , store_all write-enable signals registers, synchronously clocked same clock.

looks basic shift-registers me.

this type of arrangement might called retiming registers if there presence purely ease routing pressure 'module'. or perhaps pipelining registers if inserted maintain specific alignment between 'value_1/value_2' , 'outputs', if latency through module changed @ point.

if control signals store_1 / store_2 /store_all infact clocks, may called synchronisation stages, although design has problems in case.

your question mixes words tangentially related digital logic timing, without being specific.