input - Inputting a smaller size vector to a Verilog Module -


i wondering happen if created module size vector declaration input, , fed smaller sized vector while instantiating later. example, create module so:

module example(input, ....);   input[15:0] input;   ...   endmodule

and instantiate later, pass smaller vector size input so:

wire[11:0] foo; example bar(foo, ....);

so happens input in case? since input supposed 16 bits, 0 pad foo on left?

the default value of wire 'z'(high-impedance). since 4 bits of inputs not connected remaining input bits [12:15] takes default value in condition remaining bits connected driving input. eliminate these kind of errors in larger rtl designs running static tool on code recommended.


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